1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method thereof, and more particularly, to a semiconductor device having a multilayer interconnection structure and manufacturing method thereof.
2. Description of the Related Art
In general, multilayered interconnection technology employs three-dimensional integrated circuits to more effectively utilize the surface area of the integrated circuits. Highly integrated memory devices having a large capacity equal to or greater than 1 gigabyte, for example, a dynamic random access memory (DRAM) device, can be designed by employing the multilayered interconnection technology.
In multilayer interconnections, active devices and interconnections have a structure in which layers are stacked, and each layer is connected by an interlevel, or interlayer, connection path such as a xe2x80x9cplugxe2x80x9d or xe2x80x9cstudxe2x80x9d. Also, a xe2x80x9clanding padxe2x80x9d or xe2x80x9ctabxe2x80x9d for assisting the alignment of the plug is formed on an underlying layer to serve as a target for a plug. Further, the landing pad is connected to an underlying circuit or interconnection, and its surface area is formed to be larger than that of the underlying circuit or interconnection. This results in a larger tolerance of the target for the plug. However, a conventional landing pad or tap assists the alignment of the plug, and due to the line width being larger than that of the stud (or plug), there is a high risk that a short-circuit may occur between neighboring circuit patterns. Thus, at present, instead of using the landing pad, a technology in which self-aligned metal interconnections are formed by an etch stopper has been suggested.
FIG. 1 is a sectional view of a conventional multilayer metal interconnection structure including a stud and an etch stopper, as disclosed in U.S. Pat. No. 5,891,799. Referring first to FIG. 1, a metal interconnection 102 is formed on a semiconductor substrate 100. A first interlevel dielectric (ILD) layer 104 composed of silicon dioxide (SiO2) and a first etch stopper 106 composed of silicon nitride (Si3N4) are sequentially formed on the semiconductor substrate 100 on which the metal interconnection 102 is formed. Next, lower stud holes 108a and 108b are formed by patterning the first etch stopper 106 and the first ILD layer 104 to expose the metal interconnection 102 and the semiconductor substrate 100. Next, the lower stud holes 108a and 108b are filled with a metal material to form lower studs 110a and 110b. A second ILD layer 112 and a second etch stopper 114 are sequentially formed on the resultant of the semiconductor substrate 100 on which the lower studs 110a and 110b are formed. Next, upper stud holes 116a and 116b are formed by etching the second etch stopper 114 and the second ILD layer 112 to expose the lower studs 110a and 110b. Here, during an etching process for forming the upper stud holes 116a and 116b, the first etch stopper 106 serves as an etching reference. Next, upper studs 118a and 118b are formed in the upper stud holes 16a and 116b. 
However, the following problems arise in a conventional multilayer interconnection structure. First, in the mentioned prior art, a landing pad is not used. Thus, even though the first etch stopper 106 is used, there is a high risk that misalignment between the lower studs 110a, 110b and the upper studs 118a, 118b may occur. Meanwhile, when the landing pad is used, as described above, the distance between patterns decreases. Thus, a short-circuit can readily occur between neighboring conductive patterns.
Furthermore, a bit line of the DRAM is often used as a local interconnection on a peripheral region on which a sense amplifier is formed. In particular, since circuit layers are very densely arranged on the peripheral region, it is not easy to secure a safe distance between patterns in the horizontal direction that are formed on the same level.
Also, since the first and second etch stoppers 106 and 114 composed of silicon nitride (Si3N4) are formed on the entire resultant of the semiconductor substrate 100, excessive stress causing circuit distortion occurs in the ILD layers. Furthermore, the first and second etch stoppers 106 and 114 prevent impurities such as carbon (C), fluorine (F), and chlorine (Cl), which are contained in the ILD layers, from being outgassed during a subsequent high temperature heating process. Also, the remaining etch stoppers 106 and 114 disturb the introduction of H2 and O2 during a thermal process for reducing dangling bonds between the semiconductor substrate 100 and a gate insulating layer (not shown). As a result, the adhesion characteristics between the semiconductor substrate 100 and the gate insulating layer are adversely affected.
To address the above limitations, it is a first objective of the present invention to provide a semiconductor device capable of preventing short-circuits between neighboring conductive patterns in highly integrated circuits.
It is a second objective of the present invention to provide a semiconductor device capable of obtaining a sufficient contact margin between upper and lower studs.
It is a third objective of the present invention to provide a semiconductor device capable of preventing short-circuits between neighboring conductive patterns while obtaining a sufficient contact margin between upper and lower studs.
It is a fourth objective of the present invention to provide a semiconductor device capable of reducing stress of an interlevel dielectric (ILD) layer, caused by an etch stopper.
It is a fifth objective of the present invention to provide a semiconductor device capable of adequate outgassing of impurities while reducing stress in circuits.
It is a sixth objective of the present invention to provide a semiconductor device capable of preventing deterioration of the adhesion characteristics of a gate insulating layer and a semiconductor substrate.
It is a seventh objective of the present invention to provide a method for manufacturing the semiconductor device.
Accordingly, to achieve the first through sixth objectives, according to an aspect of the present invention, there is provided a semiconductor device. An interlevel dielectric (ILD) layer is formed on the semiconductor substrate. A first contact stud is formed in the ILD layer having a line width at an entrance portion adjacent the surface of the ILD layer larger than the line width of a contacting portion adjacent the semiconductor substrate. A second contact stud spaced apart from the first contact stud is formed in the ILD layer. It is preferable that the entrance part of the first contact stud has a line width about 30-60% larger than that of the contacting part.
Accordingly, to achieve the first through sixth objectives, according to another aspect of the present invention, there is provided a semiconductor device. An interlevel dielectric (ILD) layer is formed on the semiconductor substrate. A first contact stud having a line width of an entrance part adjacent to the surface of the ILD layer larger than the line width of a contacting part adjacent to the semiconductor substrate is formed in the ILD layer. A second contact stud spaced apart from the first contact stud is formed in the ILD layer. A landing pad having a line width larger than that of the second contact stud is formed on the ILD layer to contact the surface of the second contact stud.
It is preferable that the second contact stud has the line width of a contacting part that is entirely the same as that of an entrance part, and the entrance part of the first contact stud has a line width about 30-60% larger than that of the contacting part.
Accordingly, to achieve the first through sixth objectives, according to still another aspect of the present invention, there is provided a semiconductor device. An interlevel dielectric (ILD) layer is formed on the semiconductor substrate. A first contact stud having a line width of an entrance part adjacent to the surface of the ILD layer larger than the line width of a contacting part adjacent to the semiconductor substrate is formed in the ILD layer. A second contact stud spaced apart from the first contact stud is formed in the ILD layer. A landing pad having a line width larger than that of the second contact stud is formed on the ILD layer to contact the surface of the second contact stud. An etch stopper covers only the top and side of the landing pad.
It is preferable that the second contact stud has a line width of a contacting part that is entirely the same as that of an entrance part, and the etch stopper includes a first etch stopper formed on the landing pad and a second etch stopper formed of a spacer on both sidewalls of the landing pad, and the entrance part of the first contact stud has a line width about 30-60% larger than that of the contacting part.
It is also preferable that a plurality of gate electrodes are arranged adjacent to each other between the semiconductor substrate and the ILD layer, and self-aligned plugs are formed between the gate electrodes, and a third contact stud contacting the self-aligned plugs formed in the ILD layer. Here, it is preferable that the depth of the entrance part of the first contact stud is equal to or slightly greater than that of the third contact stud.
The semiconductor substrate is defined by a cell region and a peripheral region, the third contact stud is formed on the cell region, and the first contact stud is formed on the peripheral region.
Accordingly, to achieve the seventh objective, there is provided a method for manufacturing a semiconductor device. An interlevel dielectric (ILD) layer is formed on a semiconductor substrate. Next, a first stud hole having a line width of an entrance part adjacent to the surface of the ILD layer larger than the line width of a contacting part adjacent to the semiconductor substrate is formed in the ILD layer. Subsequently, a second stud hole to be spaced apart from the first stud hole is formed in the ILD layer. Next, first and second contact studs are formed by filling the first stud hole and the second stud hole with a conductive material.
Here, a first stud hole and a second stud hole can be formed by the following method. First, a plurality of first holes for etching a portion of the ILD layer to a shallower depth than that of the ILD layer are formed. Subsequently, a plurality of second holes are formed by etching part of the ILD layer positioned under the first hole selected from the plurality of first holes and a portion of the ILD layer on which the plurality of first holes are not formed and exposing the semiconductor substrate.
It is preferable that a photoresist pattern is formed on the ILD layer on which the plurality of first holes are formed, while covering internal sidewalls of the selected first hole, which exposes other portions of the ILD layer. Next, the ILD layer is etched to have the shape of the photoresist pattern. Before forming the ILD layer on the semiconductor substrate, gate electrodes are formed on the semiconductor substrate, and self-aligned contact plugs are formed between the gate electrodes. Here, portions selected from self-aligned contact plugs are exposed simultaneously with forming a plurality of first holes. Also, the first holes are formed to a depth equal to or deeper than the distance from the surface of the ILD layer to the surface of the contact plugs.
Also, a first stud hole and a second stud hole can be formed by the following method. A plurality of first holes for etching a portion of the ILD layer and exposing a selection region of the semiconductor substrate are formed. Next, a plurality of second holes having line widths larger than those of the first holes are formed by etching the ILD layer formed on sides of the first holes selected from the plurality of first holes to a predetermined depth. Here, before forming the IDL layer on the semiconductor substrate, gate electrodes are formed on the semiconductor substrate, and self-aligned contact plugs are formed between the gate electrodes. Here, portions selected from self-aligned contact plugs are exposed simultaneously with forming a plurality of second holes. Also, the second holes are formed to a depth equal to or deeper than the distance from the surface of the ILD layer to the surface of the contact plugs.
Also, after the step of forming first and second contact studs, a conductive landing pad having a line width larger than that of the second contact stud is formed on the ILD layer to contact the second contact stud. After forming a conductive landing pad, an etch stopper is formed to cover the conductive landing pad. Here, the etch stopper is formed by the following method. That is, a first etch stopper is formed on the conductive landing pad, and a second etch stopper formed of a spacer is formed on both sidewalls of the landing pad and the first etch stopper.